1. Technical Field
Embodiments of the present disclosure relate generally to electronic circuits, and more specifically to a high-speed frequency divider and a phase locked loop that uses the high-speed frequency divider.
2. Related Art
A frequency divider is a circuit that divides the frequency of an input signal, and provides an output signal that has a lower frequency than the input signal. The division factor by which a frequency divider is to divide the frequency of an input signal may be fixed or (statically or dynamically) programmable via corresponding program signals. The range of frequencies of the input and output signals of a frequency divider typically determines the ‘speed’ of operation of the frequency divider. In general, higher the maximum frequency of input and/or output signals of a frequency divider, the higher the ‘speed’ of the frequency divider. Thus, for example, a frequency divider capable of operating with input and/or output signals in the Giga Hertz range may be viewed as a high-speed frequency divider.
Phase locked loop (PLL) circuits are often used to generate output signals synchronous with an input reference signal. The output signal is generally designed to have a frequency equaling a desired multiple of the input reference signal. In addition, the output signal is ideally in phase-lock with the input reference signal. The signals (e.g., clock signals) generated by PLLs may be provided to various external circuits (e.g., processors), as is well known in the relevant arts.
Several embodiments of the present disclosure are directed to high-speed frequency dividers and a phase locked loop that uses such high-speed frequency dividers.